Position Summary

Samsung is a world leader in Memory, LCD and System LSI technologies. We are currently looking for exceptional software and hardware talent to join our Samsung Austin R & D Center (SARC) in Austin, TX and our Advanced Computing Lab (ACL) in San Jose, CA. SARC was established in Austin, TX in 2010 to be one of Samsungs strategic investments in high performance low power ARM based device technology. Presently our GPU design teams, located in Austin (SARC) and San Jose (ACL), are developing a GPU that will be deployed in Samsung mobile and other market segments. Our System IP team located in Austin (SARC) is working on Coherent Interconnect and memory controller architectures.

Role and Responsibilities

CAD/Methodology PNR Support Engineer:

This is a senior level position where the candidate will develop and support block and top level synthesis to signoff flows PNR (place and route) in the development of Samsung state of the art GPU IP.

The candidate is tasked with supporting Synopsys Fusion Compiler synthesis and placement, clocking, hold buffer insertion, and routing. Timing and DRCs is often correlated to our signoff tools, which include Primetime and Calibre. Close work with the vendor is performed often and can include new code updates which require integration and regression before rolling out updates. Close work with team members is continuous through the year and especially around tape-outs. Crashes or flow issues need to be resolved with personal knowledge of the tool and flows and/or testcases need to be created quickly to help resolve issues. Strong background in programming tcl. Python and advanced shell scripts are helpful to develop and support flows, scripts and tools used in our operation. Good communication is necessary. Documentation is often required to be presented and posted to CODEX.

Key responsibilities include:

Develop and support full PNR flow including Signoff Flow
Develop and support PPA and RunTime (RT) enhancements
Analyze current flow and look for opportunities to enhance PPA and RT
Heavy interaction with EDA tool vendors, block owners and design leads to ensure execution of project milestones
Participate in CAD and signoff flows in both top and block design environments

Skills and Qualifications

Minimum requirements:

BSEE, Computer Engineer or comparable with at least 2+ years of direct relevant CAD experience
Solid understanding and working knowledge of the SOC/ASIC/GPU/CPU design flow with experience in taping out designs using Synopsys PNR tools and interacted on all of the PNR steps from synthesis through route.
Hands-on experience with block and full chip implementation with the latest industry PNR flows and tools
Strong scripting/programming skills in Tcl, Shell, and Python
Solid understanding of Electrical Engineering fundamentals, analytical aptitude and excellent attention to detail

Preferred candidate will possess the following:

Be in a CAD role with a successful record of supporting tape out is required
Strong communication skills, proven track record of a physical design lead, ability to influence and work with cross functional teams to achieve milestones and project targets, discipline and planning; ability to execute with high quality deliverables is a must
Experience with 10nm Finfet or smaller process nodes
Experience with design implementation of GPU/CPU/SOC tiles and full-chip implementation work with standard industry standard tools is advantageous
Ability to analyze a blocks setup and hold timing (STA), look for transition violations, solve congestion issues, solve routing DRCs; understand tech files and how it affects tool to route; correlate Fusion Compiler DRCs with Calibre. Correlate Fusion Compiler timing with Prime Time. Understand clock skew and clock latency and the quality of clock structures; Understand non default rules in routing clocks or critical nets. Be able to bring up the GUI and analyze routing issues. Help design teams surpass any issues that arise quickly during tapeout.
Strong programming skills with tcl and python for the creation of analysis support scripts and tool support
Be able to juggle multiple issues and rank them properly to their level of importance and criticality

#SARC

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