Position Summary

Role and Responsibilities

STA Engineer

This position offers challenges to work in a multi-site environment on design and STA of complex IP cores at advanced technology nodes. You will be responsible for the micro architecture, RTL design and STA of different timing critical blocks (HMs) of the memory interface PHY (DDR/LPDDR/HBM/GDDR) IP.

Responsibilities include:

Develop the architecture, create micro-architecture and detailed design documents
RTL design and custom digital design of the critical high speed Hard macro blocks
Synthesis and DFT of the critical high speed Hard macro blocks
Familiarity with custom digital design (i.e. high speed logic paths)
Timing closure of the critical high speed Hard macro blocks working with the BE team

Develop floor-planning and CTS guidelines for layout
Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure
Perform in-house quality check before P&R and after P&R

Power domain checks, CLP

Work closely with analog and validation teams to bring up silicon and fine tune and debug performance issues at high speed
Working on GLS closure with DV, PD and Modeling folks to ensure critical performance as well as timing paths are met and if some aspect of synch design techniques are used they are also validated well
Supporting the SoC teams and customers in seamless integration the IP

Skills and Qualifications

Must have BSEE or MSEE in EE with10+years of relevant experience in the following areas:

Custom digital design of CPU cores/high speed interface IP blocks

Top/block level Synthesis, Timing closure (STA)

Good Experience in DCT/DCG based Synthesis, Equivalence checks

Good experience using Primetime SI and CCD/GCA

Good understanding of Deep Sub Micron topics

Knowledge of DDR2/3/4/LPDDR2/3/4/AMBA (AXI, AHB and APB) protocols and DDR PHY interface (DFI) standard is a plus

Experience on ASIC Synthesis flow and static timing flows, Formal checking, etc. is a must

Very good in understanding and defining constraints and critical high speed path timing closure working with BE teams

Good understanding of the APR flows is desired

Exposure top/bloc level DFT is a plus

Exposure to quality processes in the context of IP design and verification is an added advantage

Ability to work/ Prior experience as a Technical Lead for a small team is a major plus

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