We are now looking for a Senior Verification Engineer!
As a member of our DGX FPGA Logic Verification Team, you will be responsible for a portion of the FPGA Design Verification, focusing on tasks such as testbench/scoreboard/stimulus development, regression debug, and coverage closure, supporting design, implementation, and system level validation/debug. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
Technical leadership role to define/plan/implement/execute verification strategy of complex FPGA design.
Ability to delve into lowest level details of FPGA design specification, implementation and it's system level impact.
Interactions with design engineers to define detailed verification scope.
Draft detailed verification testplans.
Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM.
Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
Lookout for continuous improvement of verification flows/processes.
Ability to lead and provide detailed technical guidance junior verification engineers.
Agility to work on multiple tasks/projects.
What we need to see:
Bachelors Degree or equivalent experience
8+ years of relevant experience.
Deep experience with UVM verification methodology.
Strengths in/with SystemVerilog, SVA or functional coverage.
Proficient with scripting languages like Perl and Python.
Experience with silicon bringup.
Good interpersonal skills and the ability & desire to work as a great teammate are a must.
Ways to stand out from the crowd:
Knowledge of and experience with bus interfaces such as I2C, SPI, PCIE, SMBus, USB.
Formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal).
Gate-level simulation, reset verification, contention checking experience.
Experience with Cadence LEC or Synopsys Spyglass is a plus.
With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
