What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Masters or Bachelors in EE/ECE, 4-8 years of relevant experience in VLSI domain.

Good understanding of complete ASIC PD/timing closure flow, with hands on tape out experiences. Should have experience using industry standard STA tools like Primetime, PT based tcl scripting. Should have prior experience with block and full-chip constraints development and providing guidance to RTL and PD teams to help the timing spec. Should understand the complete physical design aspects/stages related to timing closure. Any hands-on with PR would be helpful. Good understanding of Digital, CMOS, Crosstalk, OCV, IR-drop, EM, Process variations and other STA concepts. After initial flow/methodology ramp-up, should be able to operate independently and own timing closure of individual blocks/sub-systems. Good verbal and written communication skills is a must. Should be a very good team player and be able to work with very minimal guidance from Seniors after initial ramp-up.

#LN-SR4

Requisition Number:181144
Country/Region/Location:IndiaState/Province:TelanganaCity:Hyderabad
Job Function:Design