Position Summary
6G SmartNIC
Role and Responsibilities
Designing and Developing the custom SW for the Smart-NIC or DPU (Data Processing Unit) based programmable HW accelerators
Designing HW Accelerator Logic on FPGAs using High Level Program logic languages such as P4 programming, Open-CL.
Understanding the requirements of modules needed to for high speed packet switching and routing
Involve in technical decision making by closely working with data-plane protocol team and Embedded System SW team
Performance profiling of SW based implementation vs Programmable HW accelerators
Discuss and follow-up critical issues with Smart-NIC vendors and get faster resolution
Skills and Qualifications
Requirements and Qualifications:
BS/MS with 8+ years of experience in the field of data-plane protocol stack or Embedded Software development
4+ years of experience in the areas of developing SW for Programmable Smart-NICs or DPU (Data Processing Units) or any HW accelerators
1+ years of experience in implementing the PL (Programmable Logic) on FPGAs using any one High level HW descriptive languages (VHDL or Open-CL or V++)
2+ years of experience in the areas of high speed Packet switches, routers. Strong TCP/IP stack knowledge and High speed Packet routing techniques. Hands-on experience in debugging the SW at assembly instruction level. Proficiency in using HW Debuggers and Simulators.
Good to have knowledge of Serial Interfaces: PCI-express and 10G/100G Ethernet
Prior experience in the following is preferred
- Experience in using any of the HW accelerator platforms( NVIDIA's BlueFiled DPU, Xilinx Alveo Smart-NICs or any other equivalent/custom platforms)
- P4 programming environment on Xilinx's SD-Net/Vitis-Net
- Experience in CUDA and DOCA environments from NVIDIA
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